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BÿL2006 Computer Architecture Project PART 2 –Eneral Design Of The Project: Control Unit Design: Mib Design, Assignment , UOC, UK
| University | University Of Cambridge (UOC) |
| Subject | BÿL2006 Computer Architecture Project PART 2 |
GENERAL DESIGN OF THE PROJECT:
CONTROL UNIT DESIGN:
BÿL2006 COMPUTER ARCHITECTURE PROJECT PART 2 – MIB DESIGN
1. Memory-Reference Instructions:
2. Register reference instructions:
3. I/O Reference Instructions:
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Project Expectations
1. The processor unit you designed will perform all operations in the Operation column given in the tables. must be capable of being fulfilled separately.
2. The designs of AC, DR, PC, IR, INP, SC, AR registers should be made in detail. This registers must be in the number of bits shown in the figure.
3. All data buses must be designed for 4 (four) bit data transfer.
4. Carry out output (belonging to the ALU) must be calculated.
5. Create your own table similar to the table given in Table 5.6 (ANNEX-1). is required.
6. Control Unit structure must be designed logically.
7. There should be two clock inputs in the designed system. Memory and Registers are clocked differently. It must have inputs (Mem_clock=4xReg_clock)
8. Waveform outputs (University Program Vector Waveform File) should be shown.
9. The developed system performs all the above-mentioned operations without any errors. is expected.
ANNEX-1: MANO TABLE 5.6
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